1. Field of the Invention
This invention relates to interconnections between digital integrated circuits, and more particularly to interconnections between integrated circuits in high speed computers. Specifically, this invention relates to high speed computers utilizing complementary metal oxide semiconductor (CMOS) circuitry and the use of transmission lines for interconnections between CMOS circuits.
2. Description of the Prior Art
In high speed computers which incorporate a large number of integrated circuit chips, logic decisions within a chip are accomplished at an extremely high speed. In a typical integrated circuit chip, logic decisions may be made in a nanosecond or less. In addition to the speed of operations performed within the integrated circuit, however, the ultimate speed of the computer is a function of the speed at which signals can be transmitted from an output of one integrated circuit to the input of another integrated circuit. If the transmission time between chips is slow, the computer will be slow despite the high speed operation of the integrated circuit chips themselves.
One method of interconnecting chips is simply by using a plain wire. Because of the random capacitance and inductance associated with such a connection, however, the transmission time of a useful signal can be quite high. In order to eliminate signal degradation caused by random capacitance and inductance, it is desirable to use transmission lines as connectors. Transmission lines, which have the characteristic of having uniform inductance and capacitance per unit length, provide extremely high speed transmission. The propagation speed through a transmission line is equal to the speed of light, degraded by the dielectric constant of the insulator used in the transmission line. Propagation speed in a typical transmission line is about six inches per nanosecond. Therefore, it is very desireable to utilize transmission lines for interconnections between integrated circuits in a computer, particularly when the integrated circuits are spaced apart by a relatively large distance.
Prior art high speed computers have typically utilized emitter coupled logic (ECL) circuitry. ECL circuitry generally utilizes one volt signal swings, and transmission lines having a 100 ohm characteristic impedance are typically used to provide interconnections between chips. In order to provide the necessary one volt signal swing with these transmission lines, the output circuits of the ECL chips must provide a 10 milliamp drive current. Although this drive current is relatively low, the computer has the disadvantage of having high DC power dissipation ECL circuitry.
CMOS technology has several advantages over ECL which makes it attractive for use in high speed computers. Primary among these is the fact that CMOS circuits consume little or no DC power, i.e., power is required only when the circuit is switching. However, CMOS circuits typically have a five volt signal swing, and would have to provide a 50 milliamp drive current to drive a 100 ohm transmission line on a chip. Such a drive requirement corresponds to 250 milliwatts per output line. Because of this excessive power requirement, transmission lines have not been used for interconnections between CMOS chips. Instead, plain wires having associated random (or lump) capacitance have been employed, with the result being that signal propagation from the output of one chip to the input of another is quite slow. As a consequence of the impracticability of using transmission lines, CMOS circuitry typically has not been used in high speed computers, but instead is used in applications where transmission speed requirements are not critical.